Search results for "Fixed-point arithmetic"

showing 3 items of 3 documents

Multiprocessor SoC Implementation of Neural Network Training on FPGA

2008

Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…

Computer Science::Hardware ArchitectureComputer architectureApplication-specific integrated circuitComputer scienceControl reconfigurationSystem on a chipMultiprocessingField-programmable gate arrayNetwork topologyFixed-point arithmeticFPGA prototype2008 International Conference on Advances in Electronics and Micro-electronics
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SoC-Based Implementation of the Backpropagation Algorithm for MLP

2008

The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…

Computer scienceDegree of parallelismOverhead (computing)MultiprocessingParallel computingFixed-point arithmeticPerceptronNetwork topologyField-programmable gate arrayBackpropagation2008 Eighth International Conference on Hybrid Intelligent Systems
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Hardware-efficient matrix inversion algorithm for complex adaptive systems

2012

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively s…

Floating pointbusiness.industryQR decompositionsymbols.namesakeMatrix (mathematics)Gaussian eliminationVectorization (mathematics)symbolsGenerator matrixbusinessFixed-point arithmeticAlgorithmComputer hardwareMathematicsSparse matrix2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
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